DETAILS
Syntesis, is the process of converting design code in logic gates and optimizing for less area, less power and highest performance. On the other hand Sign-off STA (Static Timing Analysis) conforms on operating performance and data integrity.
content
- Understanding RTL code
- Synthesis Flow
- Smart Trade-off Criteria
- Data Path Optimization
- Area, Power, and Performance trade-offs
- Introduction to Timing
- Timing Analysis
- Timing ECO's
- Cross Talk Issue
- IR Timing Issues
- How to debug the issues during the flow
- Projects
prerequisites
- Basic electronics and Linux basics
- Passion for learning
-
Qualification
- Diploma (EE, EC, EI, CS, IT)
- B.Tech/BE/M.Tech/ME (EE, EC, EI, CS, IT)
- Any degree with Maths and Physics
- Failed students with lots of Passion (Let's work out a way)
Selection Process
- Analytical test
- Interview