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Module 1: Introduction to Synthesis and STA

• Design Flow: RTL → GDSII
• Where Synthesis and STA fit in the flow
• Tools Overview: Design Compiler, Genus, Tempus, PrimeTime
• Combinational vs Sequential Logic

Module 2: RTL Coding Guidelines

• RTL Best Practices
• Synthesizable Constructs in Verilog
• Clocking Style and Reset Schemes
• Design Partitioning and Reusability

Module 3: Logic Synthesis

• What is Logic Synthesis?
• Technology Mapping
• Gate-Level Netlist Generation
• Timing and Area Optimization
• Hands-on: Synthesize a small RTL block

Module 4: Constraints – SDC Files

• Clock Definition
• Input/Output Delays
• Generated Clocks
• False Paths, Multi-cycle Paths
• Driving Cells and Load Constraints
• Hands-on: Write and apply SDC constraints

Module 5: Static Timing Analysis (STA) Basics

• Timing Arcs and Timing Paths
• Setup and Hold Timing
• Slack Calculation
• Clock Skew, Jitter, Latency
• Understanding Reports: report_timing
• Working with Liberty Files (.lib)

Module 6: Types of Timing Paths

• Setup vs Hold Paths
• Clock-to-Q and Propagation Delays
• Input to Register, Register to Register
• Output Delay Paths
• Recovery, Removal Timing

Module 7: Advanced STA Topics

• Multi-Corner Multi-Mode (MCMM)
• Timing Exceptions (false_path, multicycle_path)
• Clock Gating Checks
• Asynchronous Paths
• STA in Physical Design

Module 8: Timing Closure Techniques

• Timing Critical Paths
• Logic Restructuring
• Retiming, Pipelining
• Buffer Insertion, Gate Sizing
• Hands-on: Close timing on failing paths

Module 9: Clock Tree & Timing Analysis

• Pre-CTS and Post-CTS Timing
• Clock Latency and Uncertainty
• Derating and Constraints Update
• Clock Tree Balancing and Optimization

Module 10: TCL Scripting for Synthesis and STA

• Introduction to TCL language and syntax
• Variables, loops, conditionals, procedures
• Using TCL in tools like DC, Genus, PrimeTime
• Automating synthesis and timing runs
• Parsing and extracting timing reports
• Hands-on: Write TCL scripts for synthesis and STA automation

Module 11: Debugging Timing Violations

• Setup Violation Debug
• Hold Violation Debug
• Path Isolation and Clock Path Debug
• Working with Timing Reports
• TCL for Analysis Automation

Module 12: Projects

• Project 1: RTL → Synthesized Netlist with timing met
• Project 2: Multi-clock Domain Design
• Project 3: Constraints Debugging on a real IP block

Tools & Labs

• Synopsys Design Compiler / Cadence Genus
• PrimeTime / Tempus for STA
• VCS/NCSim for RTL simulation
• TCL scripting for tool flow automation

Assessment & Deliverables

• Weekly Assignments and Reports
• Quizzes on Timing Paths and Constraints
• Project Submissions with timing closure
• Final Exam for Certification

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