ICLabs.in

Module 1: Introduction to Physical Design

• What is Physical Design?
• Role of a PD Engineer
• Overview of Digital Design Flow
• RTL to GDSII – Where PD fits
• QoR Metrics: Area, Timing, Power, DRC/LVS
• Introduction to PPA Trade-offs
• Tools used in PD

Module 2: Inputs to PD

• Netlist (Synthesized)
• Constraints File (SDC)
• Technology Files (.lef, .lib, .tf)
• Floorplan Guidelines
• Power Intent Files (UPF/CPF)
• DEF/Verilog Mapping
• Understanding Design Hierarchy

Module 3: Floorplanning

• Core, Die, and Utilization
• Blockages and Macros Placement
• IO Placement & Pin Assignments
• Aspect Ratio, Halo, Channels
• Floorplan Strategies
• Hands-on: Floorplan for hierarchical & flat designs

Module 4: Power Planning

• Power Domains
• Power and Ground Rings
• Power Grid Design
• Power Straps & Tap Cells
• IR Drop and EM Basics
• Hands-on: Create power grid and simulate IR drop

Module 5: Placement

• Standard Cell Placement
• Congestion Management
• Legalization & Cell Spacing
• High Fanout Net Handling
• Hands-on: Analyze congestion & placement

Module 6: Clock Tree Synthesis (CTS)

• Skew, Jitter, Latency
• Clock Gating, Buffers
• Clock Tree Structure
• Skew Optimization
• Hands-on: CTS & Skew Analysis

Module 7: Routing

• Global and Detailed Routing
• Routing Rules & Directions
• Crosstalk, Antenna Fixes
• Timing-Aware Routing
• Hands-on: Perform routing and fix DRCs

Module 8: Post-Route Optimization & Signoff

• Timing Closure
• IR Drop Fixing
• DRC/LVS Debugging
• Crosstalk & Noise Analysis
• Signoff Tools: Tempus, Calibre

Module 9: Debugging Issues in PD Flow

• Timing (Setup/Hold)
• Clock Tree Issues
• Congestion
• Routing DRCs
• Power Integrity
• Automation with TCL

Module 10: Projects (RTL to GDSII)

• Project 1: Flat Design Implementation
• Project 2: Hierarchical Design with High Macros Count

Module 11: TCL Scripting for Physical Design

• Introduction to TCL syntax
• Variables, Loops, and Procedures
• File and String Operations
• Using TCL in Physical Design tools (Innovus, ICC2)
• Automating Repetitive Tasks
• Creating Custom Reports and Filters
• Hands-on: Write TCL scripts for floorplan, placement, and timing reports

Tools & Labs

• Cadence Innovus/Synopsys ICC2/Aprisa
• TCL Scripting, Linux Environment

Assessment & Deliverables

• Weekly Assignments
• Project Reviews
• Quizzes & Certification Test

Bonus Topics (Optional)

• FinFET Design Considerations
• CDC Issues
• DFM Guidelines
• Tapeout Process

Right mentor plays a crutial role in career building, choose right one.