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Module 1: Introduction to Digital Design

• What is RTL?
• Combinational and Sequential Logic
• Flip-Flops, Latches, MUXes, Counters
• Timing Diagrams and Setup/Hold Concept

Module 2: Verilog Basics

• Module Definition
• Ports and Parameters
• Data Types and Operators
• Always Blocks: Combinational and Sequential
• Initial vs Always

Module 3: RTL Design Practices

• Non-blocking vs Blocking Assignments
• FSM (Finite State Machine) Design
• Synchronous Reset vs Asynchronous Reset
• One-Hot, Gray Encoding
• Hands-on: Design a FSM for elevator control

Module 4: Design of Common Digital Blocks

• ALU, Adders, Comparators
• Multipliers, Shift Registers
• Counters (Up/Down, Programmable)
• Memory Interface and FIFOs
• Hands-on: RTL implementation of 4-bit ALU

Module 5: Coding for Synthesis

• Synthesizable vs Non-synthesizable Constructs
• Inferring Latches, Multiplexers
• Clock Gating Techniques
• Pipeline and Retiming Friendly Coding
• Latch Avoidance Guidelines

Module 6: SystemVerilog Enhancements (Optional)

• Interfaces and Clocking Blocks
• Structs and Enums
• Assertions for RTL Debug
• Benefits over Verilog in RTL coding

Module 7: Design for Testability

• Scan Insertion Basics
• DFT Guidelines at RTL
• Boundary Scan and BIST overview
• Hands-on: Insert scan-friendly flip-flops

Module 8: RTL Simulation and Debug

• Testbench and Simulation Flow
• Waveform Viewing and Signal Debug
• Assertions and Monitors
• Linting Tools and Coding Style Checks

Module 9: TCL for RTL Automation

• Introduction to TCL Syntax
• Using TCL in RTL Flow (Sim/Synthesis)
• Automating Simulation Runs and Logs
• Hands-on: Write a TCL script to compile and simulate testbench

Module 10: RTL to Netlist Handoff

• Constraints (SDC) Introduction
• Deliverables: RTL, Constraints, Testbench
• Preparing for Synthesis
• Sign-off Checklist before handoff

Projects

• Project 1: Design and simulate a UART Transmitter
• Project 2: RTL coding of a Pipelined ALU
• Project 3: FSM-based Arbiter with priority logic

Tools and Labs

• Modelsim / QuestaSim
• Vivado / Design Compiler for Synthesis
• GTKWAVE for viewing waveforms
• Linting tools and RTL linters (Spyglass, Verilator)

Assessment and Deliverables

• Weekly RTL assignments
• Mini Projects and Code Reviews
• Simulation results and waveforms
• Final Exam and Viva

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