DETAILS
ASIC RTL Design, Developing architecture and coding of required functionality of the SOC (system-on-chip). The code should be synthesizable to gate level which later can be consider for ASIC development.
Content
- Understanding RTL code
- Synthesis Flow
- Smart Trade-off Criteria
- Data Path Optimization
- Area, Power, and Performance trade-offs
- Introduction to Timing
- Timing Analysis
- Timing ECO's
- Cross Talk Issue
- IR Timing Issues
- How to debug the issues during the flow
- Projects
prerequisites
- Basic electronics and Linux basics
- Passion for learning
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Qualification
- Diploma (EE, EC, EI, CS, IT)
- B.Tech/BE/M.Tech/ME (EE, EC, EI, CS, IT)
- Any degree with Maths and Physics
- Failed students with lots of Passion (Let's work out a way)
Selection Process
- Analytical Test
- Interview