ICLabs.in

Module 1: Verification Basics

• What is Verification?
• Importance in ASIC/SoC Design Flow
• Verification Metrics: Coverage, Bug Rate
• Types: Simulation, Formal, Emulation, FPGA

Module 2: Testbench Architecture

• Stimulus, DUT, Monitor, Checker
• Scoreboard and Reference Models
• Self-checking Testbenches
• Testbench Topology

Module 3: SystemVerilog for Verification

• Data Types and Constructs
• Randomization Techniques
• Tasks and Functions
• Classes and Inheritance
• Queues, Mailboxes, Semaphores

Module 4: Assertions (SVA)

• Immediate vs Concurrent Assertions
• Assertion Syntax and Examples
• Cover Properties
• Binding Assertions to RTL
• Debugging Failing Assertions

Module 5: Constrained Random Verification

• Constraint Blocks
• Randomization in Classes
• Controlling Random Behavior
• Functional Coverage Basics

Module 6: UVM Fundamentals

• Overview of UVM Components
• UVM Testbench Architecture
• UVM Macros and Factory
• Building UVM Environments
• UVM Phases

Module 7: UVM Testcases and Sequences

• Creating Sequences and Drivers
• Config DB and Virtual Sequences
• Scoreboard and Coverage Collection
• Testcases for Feature and Corner Cases

Module 8: Coverage Analysis

• Code Coverage: Line, Toggle, FSM
• Functional Coverage: Covergroups
• Merging Coverage Results
• Generating Coverage Reports
• Coverage Closure Strategies

Module 9: Debugging and Simulation

• Waveform Debugging in DVE/SimVision
• Assertion Failure Analysis
• Scoreboard Mismatches
• RTL Signal Trace and Logging
• Fixing Deadlocks and Missed Events

Module 10: TCL Automation for Simulation

• Using TCL with VCS/QuestaSim
• Automating Regression Suites
• Parsing Logs and Result Filtering
• Hands-on: Build TCL for testcase compilation and execution

Projects

• Project 1: Verification of FIFO with assertions and coverage
• Project 2: UVM testbench for UART or SPI
• Project 3: Complete Verification Plan and Report

Tools and Labs

• Synopsys VCS, Cadence Xcelium, Mentor QuestaSim
• UVM Reference Library
• GTKWave, DVE, SimVision
• Code coverage and functional coverage tools

Assessment and Deliverables

• Weekly verification assignments
• Final UVM testbench submission
• Coverage and assertion-based report
• Viva and certification test

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