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Module 1: Introduction to Power in VLSI

• Types of power: Dynamic, Static (Leakage), Short-Circuit
• Impact of Power on Design QoR
• Why Power Analysis and Sign-off is Critical
• Power vs Performance vs Area trade-offs

Module 2: Power Basics and Terminology

• Dynamic Power Equation
• Leakage Mechanisms (Subthreshold, Gate leakage)
• Voltage, Capacitance, Frequency Impact
• Introduction to UPF and CPF

Module 3: Power Intent and RTL Guidelines

• Multi-Voltage Designs
• Power Domain Definitions
• Retention, Isolation, Level Shifters
• RTL coding best practices for low power
• Hands-on: Create and simulate UPF-based RTL design

Module 4: Power Estimation at RTL and Gate Level

• Vector-based vs Vectorless Power Estimation
• Activity Files: SAIF, VCD, FSDB
• RTL Power Estimation
• Gate-level Power Estimation
• Annotation of switching activity

Module 5: Dynamic Power Analysis

• Cycle-accurate activity capture
• Power Profiles across cycles
• Hotspot identification
• Hands-on: Run dynamic power analysis with PTPX/Voltus

Module 6: Leakage Power Analysis and Optimization

• Leakage sources and modeling
• Threshold Voltage and Multi-Vt Techniques
• Power Gating Strategy
• Sleep Modes and Clock Gating
• Hands-on: Report leakage using RTL and gate-level flows

Module 7: IR Drop Analysis

• Static vs Dynamic IR Drop
• Power Grid Design and Checks
• Voltage Drop Hotspots
• Impact on Timing and Functionality
• Hands-on: IR analysis using RedHawk or Voltus

Module 8: EM (Electromigration) Analysis

• Basics of EM and its impact
• Current Density Limits
• Pin/Net EM Failures
• Tool Flow for EM Checks
• Hands-on: Run EM reports and identify critical nets

Module 9: Power-Aware STA and Sign-off

• Power-Aware Synthesis and Timing
• Voltage Scaling and PVT Corners
• Sign-off Views and MCMM
• Multi-voltage timing paths
• Hands-on: Run STA with UPF and voltage-aware setup

Module 10: Power Sign-off Reports and Debug

• Reading Power Reports
• Hierarchical vs Flat Reporting
• IR/EM Violation Debug
• Power vs Performance Closure
• Sign-off Checklist

Module 11: TCL Automation for Power Flows

• TCL for PTPX, Voltus, Redhawk
• Report Generation and Filtering
• Parsing SAIF/VCD reports using TCL
• Hands-on: Automate IR/EM reports with scripts

Module 12: Projects and Case Studies

• Project 1: RTL power estimation and optimization
• Project 2: Gate-level IR/EM analysis and fixes
• Project 3: Power-aware STA and closure

Tools and Labs

• Cadence Voltus, Synopsys PTPX, Ansys RedHawk
• Liberty files, activity files (SAIF, VCD)
• UPF/CPF support
• Custom reporting scripts with TCL

Assessment and Deliverables

• Weekly Assignments and Lab Reports
• Project Reviews and Demos
• Final Quiz on Power Sign-off flow
• Power Debug Viva and Certificate

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