“Tell me and I forget, teach me and I may remember, involve me and I learn.” – Benjamin Franklin
Course information
- Category: VLSI Frontend
- Duration: 6 to 8 Months
- Timings: 9AM to 5PM
- Mode: Offline
We guarantee your Learning and Placement
Details
ASIC RTL Design, Developing architecture and coding of required functionality of the SOC (system-on-chip). The code should be synthesizable to gate level which later can be consider for ASIC development.
Content
- >> Digital Basics
- >> Combinational Cells
- >> Sequential Cells
- >> FSM Design
- >> Verilog/System Verilog
- >> MicroArchitecture
- >> Coding
- >> FPGA implementation flow
- >> Constraints development
- >> Timing Analysis
- >> How to debug the issues during the flow
- >> Projects
Prerequisite
- >> Passion for learning
- >> Qualification
- >> Diploma (EE,EC,EI,CS,IT)
- >> B.Tech/BE/M.Tech/ME (EE,EC,EI,CS,IT)
- >> Any degree with Maths and Physics
- >> Failed students with lots of Passion (Let's work out a way)
Selection Process
- >> Analytical test
- >> Interview
**Get up to 50% sponsorship when you out perform in the test and interview [purely decided by sponsoring company]
Limited Seats - 1 to 1 training (pretty new right)
Training calendar
Contact Info
- Email: info@iclabs.in
- Ph/What's App: +91 80 5062 3065
- Click here to Fill the Form
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Fee Details
Let's discuss togetherTrainer
- Harshit (Module Trainer)
- Experience: 4+ Years
- Skill Set: RTL Development
- Suprevisor: PRASAD (Chief Trainer)
- Experience: 18+ Years
- Skill Set: RTL to GDS II