info@iclabs.in +91 80 5062 3065
fpga-programming-using-xilinx

    “Tell me and I forget,
      teach me and I may remember,
      involve me and I learn.”
    – Benjamin Franklin

Course information

  • Category: VLSI Frontend
  • Duration: 6 to 8 Months
  • Timings: 9AM to 5PM
  • Mode: Offline/Online
We guarantee your Learning and Placement

Details

ASIC RTL Design, Developing architecture and coding of required functionality of the SOC (system-on-chip). The code should be synthesizable to gate level which later can be consider for ASIC development.

Content

  •   >>   Digital Basics
  •   >>   Combinational Cells
  •   >>   Sequential Cells
  •   >>   FSM Design
  •   >>   Verilog/System Verilog
  •   >>   MicroArchitecture
  •   >>   Coding
  •   >>   FPGA implementation flow
  •   >>   Constraints development
  •   >>   Timing Analysis
  •   >>  How to debug the issues during the flow
  •   >>  Projects

Prerequisite

  •   >>   Passion for learning
  •   >>  Qualification
    •     >>  Diploma (EE,EC,EI,CS,IT)
    •     >>  B.Tech/BE/M.Tech/ME (EE,EC,EI,CS,IT)
    •     >>  Any degree with Maths and Physics
  •   >>  Failed students with lots of Passion (Let's work out a way)

Selection Process

  •   >>  Analytical test
  •   >>  Interview

**Get up to 50% sponsorship when you out perform in the test and interview [purely decided by sponsoring company]

Limited Seats - 10 people per batch

Training calendar

Contact Info

  • Email: info@iclabs.in
  • Ph/What's App: +91 80 5062 3065
  • Click here to Fill the Form

Fee Details

Course Fee:

Discounted Fee:

Trainer

  • Harshit (Module Trainer)
  •  Experience: 4+ Years
  •  Skill Set: RTL Development
  • Suprevisor: PRASAD (Chief Trainer)
  •  Experience: 16+ Years
  •  Skill Set: RTL to GDS II