info@iclabs.in +91 80 5062 3065

    “Tell me and I forget,
      teach me and I may remember,
      involve me and I learn.”
    – Benjamin Franklin

Course information

  • Category: VLSI DFx
  • Duration: 5 to 7 Months
  • Timings: 9AM to 5PM
  • Mode: Offline/Online
We guarantee your Learning and Placement

Details

Design for Testability is a process of finding manufacturing faluts in a chip by inserting some self testing logic into the design. The amount of logic we insert is directly propotional to the chip size. Containing area at a specific number with highest test coverage is a challenge.

Content

  •   >>   Digital Design
  •   >>   Inputs to DFT
  •   >>   Understanding netlist
  •   >>   Scan
  •   >>   Compression
  •   >>   ATPG
  •   >>   Test coverage analysis
  •   >>   Improve test coverage
  •   >>   Introduction to MBIST, JTAG
  •   >>  How to debug the issues during the flow
  •   >>  Projects

Prerequisite

  •   >>   Passion for learning
  •   >>  Qualification
    •     >>  Diploma (EE,EC,EI,CS,IT)
    •     >>  B.Tech/BE/M.Tech/ME (EE,EC,EI,CS,IT)
    •     >>  Any degree with Maths and Physics
  •   >>  Failed students with lots of Passion (Let's work out a way)

Selection Process

  •   >>  Analytical test
  •   >>  Interview

**Get up to 50% sponsorship when you out perform in the test and interview [purely decided by sponsoring company]

Limited Seats - 10 people per batch

Training calendar

Contact Info

  • Email: info@iclabs.in
  • Ph/What's App: +91 80 5062 3065
  • Click here to Fill the Form

Fee Details

Course Fee:

Discounted Fee:

Trainer

  • Malli (Module Trainer)
  •  Experience: 10+ Years
  •  Skill Set: DFT
  • Suprevisor: PRASAD (Chief Trainer)
  •  Experience: 16+ Years
  •  Skill Set: RTL to GDS II