info@iclabs.in +91 80 5062 3065
cmos-standard-cell-layout-online

    “Tell me and I forget,
      teach me and I may remember,
      involve me and I learn.”
    – Benjamin Franklin

Course information

  • Category: VLSI Analog
  • Duration: 4 to 6 Months
  • Timings: 9AM to 5PM
  • Mode: Offline/Online
We guarantee your Learning and Placement

Details

Standard Cell Layout, Foundation IPs plays important role in semi custom flows, having layout for optimized area, power and performance is key for ASIC success.

Content

  •   >>   Device basics
  •   >>   Layout basics, PDK
  •   >>   Stick dagrams and layout techniques
  •   >>   Layout matching techniques
  •   >>   Area estimation and floorplan
  •   >>   Layout failure machanism
  •   >>   Physical Verificaiton
  •   >>  How to debug the issues during the flow
  •   >>  Projects

Prerequisite

  •   >>   Passion for learning
  •   >>  Qualification
    •     >>  Diploma (EE,EC,EI,CS,IT)
    •     >>  B.Tech/BE/M.Tech/ME (EE,EC,EI,CS,IT)
    •     >>  Any degree with Maths and Physics
  •   >>  Failed students with lots of Passion (Let's work out a way)

Selection Process

  •   >>  Analytical test
  •   >>  Interview

**Get up to 50% sponsorship when you out perform in the test and interview [purely decided by sponsoring company]

Limited Seats - 10 people per batch

Training calendar

Contact Info

  • Email: info@iclabs.in
  • Ph/What's App: +91 80 5062 3065
  • Click here to Fill the Form

Fee Details

Course Fee:

Discounted Fee:

Trainer

  • Sunil (Module Trainer)
  •  Experience: 8+ Years
  •  Skill Set: Layout Design
  • Suprevisor: PRASAD (Chief Trainer)
  •  Experience: 16+ Years
  •  Skill Set: RTL to GDS II