“Tell me and I forget, teach me and I may remember, involve me and I learn.” – Benjamin Franklin
Course information
- Category: VLSI backend
- Duration: 4 to 6 Months
- Timings: 9AM to 5PM
- Mode: Offline/Online
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Details
Syntesis, is the process of converting design code in logic gates and optimizing for less area, less power and highest performance. On the other hand Sign-off STA (Static Timing Analysis) conforms on operating performance and data integrity.
Content
- >> Understanding RTL code
- >> Synthesis Flow
- >> Smart Trade-off Criteria
- >> Data Path Optimization
- >> Area, Power and Performance trade-offs
- >> Introduction to Timing
- >> Timing Analysis
- >> Timing ECO's
- >> Cross Talk Issue
- >> IR Timing Issues
- >> How to debug the issues during the flow
- >> Projects
Prerequisite
- >> Basic electronics and Linux basics
- >> Passion for learning
- >> Qualification
- >> Diploma (EE,EC,EI,CS,IT)
- >> B.Tech/BE/M.Tech/ME (EE,EC,EI,CS,IT)
- >> Any degree with Maths and Physics
- >> Failed students with lots of Passion (Let's work out a way)
Selection Process
- >> Analytical test
- >> Interview
Limited Seats
Training calendar
Contact Info
- Email: info@iclabs.in
- Ph/What's App: +91 80 5062 3065
- Click here to Fill the Form
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Trainer
- PRASAD (Chief Trainer)
- Experience: 18+ Years
- Skill Set: RTL to GDS II