info@iclabs.in +91 80 5062 3065

    “Tell me and I forget,
      teach me and I may remember,
      involve me and I learn.”
    – Benjamin Franklin

Course information

  • Category: VLSI backend
  • Duration: 3 to 4 Months
  • Timings: 9AM to 5PM
  • Mode: Offline/Online
We guarantee your Learning and Placement

Details

Syntesis, is the process of converting design code in logic gates and optimizing for less area, less power and highest performance. On the other hand Sign-off STA (Static Timing Analysis) conforms on operating performance and data integrity.

Content

  •   >>   Understanding RTL code
  •   >>   Synthesis Flow
  •   >>   Smart Trade-off Criteria
  •   >>   Data Path Optimization
  •   >>   Area, Power and Performance trade-offs
  •   >>   Introduction to Timing
  •   >>   Timing Analysis
  •   >>   Timing ECO's
  •   >>   Cross Talk Issue
  •   >>   IR Timing Issues
  •   >>  How to debug the issues during the flow
  •   >>  Projects

Prerequisite

  •   >>   Passion for learning
  •   >>  Qualification
    •     >>  Diploma (EE,EC,EI,CS,IT)
    •     >>  B.Tech/BE/M.Tech/ME (EE,EC,EI,CS,IT)
    •     >>  Any degree with Maths and Physics
  •   >>  Failed students with lots of Passion (Let's work out a way)

Selection Process

  •   >>  Analytical test
  •   >>  Interview

**Get up to 50% sponsorship when you out perform in the test and interview [purely decided by sponsoring company]

Limited Seats - 10 people per batch

Training calendar

Contact Info

  • Email: info@iclabs.in
  • Ph/What's App: +91 80 5062 3065
  • Click here to Fill the Form

Fee Details

Course Fee:

Discounted Fee:

Trainer

  • PRASAD (Chief Trainer)
  • Experience: 16+ Years
  • Skill Set: RTL to GDS II